Technische Universität München Robotics and Embedded Systems
 

Dr. Hardik Shah

 

Research Assistant

E-Mail shah@in.tum.de
Room Schleißheimerstr. 90a
Phone +49.89.289.18082
Fax +49.89.289.18107
Address Institut für Informatik VI
Technische Universität München
Schleißheimer Str. 90A
85748 Garching bei München
Germany
Homepage http://www6.in.tum.de/Shah/
hardik Shah
 

Teaching

Projects

Curriculum Vitæ

Current Research Interests

Demos

Publications

[1] Hardik Shah, Kai Huang, and Alois Knoll. Timing anomalies in multi-core architectures due to the interference on the shared resources. In Design Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific, pages 708-713, Jan 2014. [ .bib | .pdf ]
[2] Hardik Shah, Andrew Coombes, Andreas Raabe, Kai Huang, and Alois Knoll. Measurement based wcet analysis for multi-core architectures. In RTNS 2014, Versailles, France, 2014. [ .bib | .pdf ]
[3] Hardik Shah, Kai Huang, and Alois Knoll. The priority division arbiter for low wcet and high resource utilization in multi-core architectures. In RTNS 2014, Versailles, France, 2014. [ .bib | .pdf ]
[4] Kai Huang, Hardik Shah, Karan Savant, Dexin Chen, Gang Chen, Sebastian Klose, and Alois Knoll. A lego/fpga-based platform for the education of cyber-physical/embedded systems. In Workshop on Embedded and Cyber-Physical Systems Education (WESE), October 2013. [ .bib | .pdf ]
[5] Hardik Shah, Andreas Raabe, and Alois Knoll. Challenges of WCET analysis in COTS multi-core due to different levels of abstraction. In hiRES 2013, Berlin, 2013. [ .bib | .pdf ]
[6] Hardik Shah, Alois Knoll, and Benny Akesson. Bounding resource interference: Detailed analysis vs. latency-rate analysis. In Design, Automation and Test in Europe (DATE), Grenoble, 2013. [ .bib | .pdf ]
[7] Hardik Shah, Kai Huang, and Alois Knoll. Weighted execution time analysis of applications on cots multi-core architectures. Technical Report TUM-I1339, 2013. [ .bib | .pdf ]
[8] Hardik Shah, Andreas Raabe, and Alois Knoll. Bounding WCET of applications using SDRAM with priority based budget scheduling in MPSoCs. In Design, Automation Test in Europe Conference Exhibition (DATE), 2012, pages 665-670, March 2012. [ DOI | .bib | .pdf ]
[9] Hardik Shah, Andreas Raabe, and Alois Knoll. Dynamic priority queue: An SDRAM arbiter with bounded access latencies for tight WCET calculation. CoRR, 1207-1187, 2012. [ .bib | .pdf ]
[10] Andreas Raabe, Hardik Shah, and Anton Hattendorf. Mehrkernsysteme für safety-kritische Echtzeitsysteme. In Embedded Software Engineering Kongress, 2012. [ .bib | .pdf ]
[11] Hardik Shah, Andreas Raabe, and Alois Knoll. Priority division: A high-speed shared-memory bus arbitration with bounded latency. In Design, Automation Test in Europe Conference Exhibition (DATE), 2011, pages 1-4, March 2011. [ .bib | .pdf ]